Industria dei semiconduttori, tecnologie, progettazione: stato attuale e sviluppi futuri

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1 Industria dei semiconduttori, tecnologie, progettazione: stato attuale e sviluppi futuri Ing. Michele Taliercio CR&D - External R.& D. Program Coordinator Crema, 14 Maggio 2001 STMicroelectronics

2 Industria dei semiconduttori Mercato Tecnologia Progettazione Fabbrica Fattore umano

3 Industria dei semiconduttori, tecnologie, progettazione: stato attuale e sviluppi futuri 1) Il mercato 2) La tecnologia 3) La progettazione 4) La fabbrica 5) Il fattore umano

4 Semiconductor market cycles beyond 2000, long term trend $ Billions : $204B 1990 : $50B 1980 : $10B MARKET CAGR % : 15% over 40 years 15% over last 10 years 7% over last 5 years % Growth 75% % 50% % Growth 2000 market Current Market Trend Line Source : WSTS, ST % 0% -25% 8

5 NEW MARKET DRIVING FORCES GROWING SEMICONDUCTOR CONTENT IN ELECTRONIC EQUIPMENT 1965 : 2% 1975 : 4% 1985 : 7% 1995 : 20% 2005 : 25% Main Frame Defense Mid-frame Industrial PC Motherboard Communication Portability Connectivity $400B in 2005 Infrastructure Productivity Corporation Productivity 12" $204B Individual Productivity Commodities Bipolar 2" $1.5B 4" $4B Mem, Micro, Asic Cmos 6" $25B 8" $144B System-on-chip Cmos, Mixed Power % 16%

6 Weather Manual on line Rear View Camera 2010 ELECTRONICS IN THE CAR Drive assistance DRIVER INFORMATION SYSTEM GPS Web traffic Camera Messaging BODY Climate Power seats Lighting Door control MOTOR Engine Transmission Regulator Internet/Games Radio/phone TV/DVD DVD changer ENTERTAINMENT Emergency call SAFETY ABS ASR AirBag Power Steering the Car is connected to the World

7 2010 Electronics on individual Permanent portable electronics : communication (UMTS, ) leisure (games, music, video, ) work (data processing, ) health monitoring Picture : Siemens + Private data identification mobility tools (GPS, )

8 2010 Generalized e-commerce Home purchases Street purchase Office purchase Mobile purchase Source : Siemens Paying by mobile phone, by calling the number of the machine

9 The development of microelectronics is at the very heart of economic development Banking systems Research Services Government action Leisure Computers Communications Medical systems Microelectronics Electronics Education Industry Environment Transportation

10 Size and price reduction for electronic functions Voice recognition $ Image compression Voice recognition $ $ Image compression Communication protocol Processing power Communication protocol Processing power

11 Economic Impact - Value Added An Industry Built On Sand 10 6 Value Added Chain Sand <$1/kg Polysilicon $50/kg 200mm Prime Wafer $1,400/kg 200mm Processed Wafer $25,000/kg Packaged Integrated Circuit $ /kg Generating End Equipment Worth $500,000/kg With A Street Value Of More Than $1,000,000/kg That s What Makes Microelectronics So Important MEDEA Forum 99 Slide 8

13 History 1897 Discovery of the electron (J. Thomson) 1907 First termoionic valve (L. De Forest) 1948 First transistor (W. Shockley, J. Bardeen, W. Brattain) 1958 Integrated circuit 1962 MOS transistor Kb DRAM memory bit microprocessor... 80s CMOS convergence bit microprocessor Mb DRAM (16 Mb production) Mb DRAM (64 Mb production) Gb DRAM (256 Mb production) Central R&D Genova, November 10th, 2000

14 CMOS Integration Trend: Moore s Law Transistors /chip 10G 1G 100M 10M 1M 100K 10K 4 Kb Central R&D 16 Kb Memory (DRAM) 64 Kb 256 Kb Mb 1 Mb Mb 64 Mb PII Pentium 80486,680 Microprocessor 1 Gb 256 Mb R&D - Jan 2000 COMPANY CONFIDENTIAL J.Monnier PIII 4 Gb Power K

15 ITRS Roadmap Potential Acceleration SIA Minimum Feature Size (nm) (DRAM Half-Pitch) ISMT Litho 2000 Plan 1997 SIA Area for Future Acceleration 1998 / 1999 ITRS ST 8/31/00 GF 5

16 Index [log] ,20 $ / Mbit 1Tbit Complessità (bit-volume) x cm² Dimensioni del chip x 8 1 0, DRAM Prezzo/Mbit 0,66cts/Mbit x 1/ Mbit 18 ans 1Gbit 4Gbit 16Gbit 64Gbit 256Gbit Tbit Complessità in bit Geometrie in nm Fonte: ITRS, MEDEA

17 The Optical Lithography perspective Determining the limits of today state of the art photolithography nm nm nm nm nm nm MOS & Interconnect SK SK WR WR HWR BH Contact SK WR HWR HWR BH BH Solutions Known Work Required Hard Work Required Black Hole Source: SEMATECH

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21 Interconnect Challenges As technology scales, wires, not devices, dominate the delay, power and size of integrated circuits Interconnect trends Technology generation (nm) metal levels (number) max interconnect length (Km) Copper, instead of Al, and low K dielectric Below 100nm not known solutions to meet performance requirements Design and layout solutions managing signal delay on a local scale are needed Central R&D Genova, November 10th, 2000

22 VLSI Process Evolution 2 Year acceleration of technology nodes : 70 nm for DRAM and 45 nm for MPU in 2008 (ITRS) Lithography reaching optical limits New front-end / back-end materials needed Interconnect challenge below 100 nm Defect control: exponentially growing difficulty Technology modeling and new simulation tools Central R&D Genova, November 10th, 2000

23 VLSI Process Evolution Major non incremental changes : SiGe introduction 1999 Copper replacing Aluminum mm transition 2001 SiO 2 evolving to low K dielectric 2002 High K deposited gate dielectric 2003 Gate electrode poly replacement 2007 Non-optical lithography intercept 2007 Central R&D Genova, November 10th, 2000

24 CMOS Derivatives DIFFERENTIATED PROCESS VARIANTS BY APPLICATION BICMOS! RF(cellular phone)! Fiber Optic IC Analog! Tuner(Set-Top Box) RFCMOS! Bluetooth HFCMOS! Power Management (Cellular phone) Imager! Web Cam SRAM/DRAM! PC peripherals CMOS CORE PROCESS

25 Non Volatile Memories (NVM) derivatives DIFFERENTIATED PROCESS VARIANTS BY APPLICATION Multilevel Flash embedded! MP3 Flash embedded! Automotive peripherals EEPROM embedded! Smartcard OTP/EPROM embedded! GPS CMOS NVM CORE PROCESS

26 Transistor, a silicon perspective M1 : W MOS STI 1 µm MOS poly gate length = 0.25 µm, Shallow Trench Isolation Metal 1 and contact

27 Metal1, a silicon perspective CMOS 0.25 µm, Shallow Trench Isolation, M1 : Metal1

28 MOS & inteconnections, silicon perspective M6 : Al Via5 : Al M5 : Al Via4 : Al M4 : Al Via3 : W M3 : Al Via2 : W M2 : Al Via1 : W M1 : W Contact : W CMOS 0.25 µm, STI, 5 Metal Layer with CMP, M6 for bump

29 Interconnect Delay versus Dielectric K for Al and Cu Normalized Delay Al Cu Dielectric K

31 Technology platform for System-On-A-Chip Concurrent Engineering Process & options development Pilot line Production UNICAD tools & methods Cores : µp, DSP, RAM, ROM,... Technology Platform System prototype HW - SW codesign & IP reuse Central R&D Time to Market & flexibility Early access for customers to new prototypes R&D - Jan 2000 COMPANY CONFIDENTIAL J.Monnier

32 Complex VLSI : Challenges Manage the Complexity System-on-chip design Design Reuse HW/SW Co-design Testing System on a Chip Millions of Gates < 0.18 µm Geometries Manage the Performance Critical dimensions Power Physical Design Reliability Central R&D R&D - Jan 2000 COMPANY CONFIDENTIAL J.Monnier

33 SOC AT THE HEART OF CONFLICTING TRENDS Time-to-market Process roadmap acceleration Consumerization of electronic devices Link FEI Dolby AC3 Denc ST20 MPEG2 Video Complex systems ucs, DSPs HW/SW SW protocol stacks RTOS Digital/Analog IPs On-Chip busses 2 x 3 DAC Deep sub micron effects crosstalk electro migration wire delays mask costs (OPC, PSM)

34 ACCELERATION OF TIME Years B&W TV Color TV VCR TIME TO 10 MILLION UNITS PC GSM STB DVD In 2010, instant 10 Million Units volumes will be required

35 SoC Implementation Platform Cell Libraries Link FEI ST20 IP Blocks Design Tools Dolby AC3 Denc 2 x 3 DAC MPEG2 Video Data Management Central R&D Flows Kits & Methods R&D - Jan 2000 COMPANY CONFIDENTIAL J.Monnier

36 THE DESIGN PRO D UCTIVITY GAP Logic Transistors per Chip (M) CAGR 58% CAGR 21% Productivity (K)Trans./Staff-Mo Source ITRS roadmap 1999

37 Process / Design Gap Design Complexity Process Capability (tr. count linear) System Level Entry HW-SW Methodologies + 60% / year IP Reuse + 20% / year RTL-to-Layout Flow Analog & Full-Custom Design Year Source : ST Central R&D R&D - Jan 2000 COMPANY CONFIDENTIAL J.Monnier

38 From System Level down to Silicon, the needs Complement the rich, heterogeneous process technology offer with tools/methods supporting it at architecture and system design levels System Level Entry HW-SW Methodologies RTL-to-layout Flow DSP algorithms, Protocols, Control, Real-time, GUI Executable specifications, system validation DO THE RIGHT THING Processors, memories, logic, datapaths, analog, RF, A/D Virtual prototype, Architecture exploration HW/SW co-verification (co-simulation, co-emulation) High performance S/W compilation DO THE THING RIGHT, FAST Logic, analog, DRAM, SRAM, Flash, High-speed, Power DO IT IN ON A SINGLE CHIP! Process capabilities

39 CONCLUSION :DEEP SU B MICR O N SOC DESIGN PLATFORMS Application Sensors DRAM CORE DSP CLOCK GEN U A R T J T A G I/O (serial) Fast Prototyping System-Level platform STBUS RF RAM ROM Logic efpga SOC core-std. CMOS logic (Bluetooth, PicoRadio) Flash SOC Process SOC Design Platform

40 Industria dei semiconduttori, tecnologie, progettazione: stato attuale e sviluppi futuri 1) Il mercato 2) La tecnologia 3) La progettazione I Prodotti 4) La fabbrica 5) Il fattore umano

41 µm 0.15 M tr/cm2 1 ML / 5 V 100 mm µm 1.5 M tr/cm2 3 ML / 3.3 V 200 mm µm 15 M tr/cm2 7 ML / 1.5 V 300 mm ( start of prototyping) Central R&D R&D - Jan 2000 COMPANY CONFIDENTIAL J.Monnier

42 Evolution of Design Methodology CD's (nm) Standard cells RC for Clocks Dig. libraries RC for all nets Signal isolation INTERCONNECT Block reuse Leakage Crosstalk FlipChip RLC parasitics Block protocols Package simul. Power solution New analog des. New tools & methodology Increased design complexity POWER Appli. specif. platform Combined P&R/synth. New device models Gate current Transmission line eff. Soft errors Current switch Substrate coupling RELIABILITY Years Block communication Signal skew New faults models Signal integrity Local thermal variation Interco. skin effects Source barrier effects Quantum effects New BIST... 10/05/01

43 STPC industrial PC-ON-CHIP System On Chip X86 Core TFT controller 64-bit Graphics Engine 64-bit Memory controller PCMCIA (Cardbus) PCI & ISA controller Keyboard & Mouse controller Serial & parallel port controller... HCMOS6-5L 140 mm² 2.5 M transistors

44 Link MPEG2 Audio Encoder RGB YUV ST20-TP2 MPEG2 Video Set-top box for DXX (STi5500) (design DPG & PPG) MPEG2 A/V : 1.3 M tr. ST20-TP2 : 2.0 M tr Link, encoder & DACs : 0.7 M tr. process HCMOS6 CMOS 0.35 µm, 5 ML 4.0 M transistors 96 mm2

45 ST10 HDD controller with Embedded DRAM (Design DPG) 1 Mbit DRAM HCMOS6 : 0.35 µm, 5 ML ST10 microprocessor & 1 Mb DRAM 1.8 M transistors 49 mm2

46 DSP952 : core, memories & peripherals SPS2 SPS2 SPS2 SPS2 program data 16 bit fixed point DSP : program memory : 32 kword data memory : 16 kword cycle time : 10 ns SPS2 program SPS2 CORE DPR2 PLL peripherals HCMOS7 : 0.25 µm, 5 ML total area : 27 mm2 core area : 1 mm2

47 ST10F bit µc with 2 Mbit Flash 0.35 µm, 5 metal levels, 48 mm 2 M5 M4 M3 M2 M1 Logic interconnection scheme M3 M2 M1 Array interconnection scheme 1.72µm² Flash Cell Central R&D April 7th, 2000

48 64Mbit Multilevel Flash Memory Technology: 0.18um CMOS triple well double poly triple metal Multilevel Concept: 2bit/cell "11" "10" "01" "00" 4 storage levels 64Mbit = 32Mcells V Read Central R&D - Non Volatile Memory Process Development

50 ST Agrate Brianza: Centro Tecnologico R2

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52 Processi Processi di lavorazione delle fette di silicio Il processo richiede circa 400 operazioni e un numero molto elevato di controlli Il tempo di ciclo della produzione è di circa 2 mesi L impianto lavora 24 h / giorno per 7 giorni / settimana Le fette finite e collaudate elettricamente vengono inviate agli stabilimenti di assemblaggio per l incapsulatura plastica

53 Agrate Brianza - R2 : Caratteristiche dell Impianto Area pulita ( clean room ) : 5600 m 2 Ricircolo dell aria 10 X / minuto Pulizia dell aria volte quella di una camera operatoria Polverosità : classe 0 (< 1 particella da 0.5 micron / m 3 ) Temperatura controllata : 22 +/ C in litografia Umidità relativa : %

54 Agrate Brianza - R2 : Caratteristiche dell Impianto Prodotti chimici, gas ultrapuri e acqua deionizzata Rete per la distribuzione e raccolta di gas e fluidi di processo Più di 20 prodotti chimici ad alta purezza controllati al punto d uso 2 edifici di servizio per la generazione di acqua deionizzata (120 m 3 / h) e prodotti chimici

56 Microelectronics is a "Global Human Challenge" The Microelectronics Industry employs around 800 thousand people worldwide In the assumption: Productivity increase of 10-20% per year Replacing turnover of around 5% per year The industry need will be: 100 thousand people per year 60 thousand highly qualified, highly specialized 40 thousand still classified as operators, but high degree of qualification is a must This Human Capital availability can be the major limiting factor to the Microelectronics growth in the year 2000 s, and primarily in the Western world