Chapter 3 Combinational Logic Design

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1 Logic and Computer Design Fundamentals Chapter 3 Combinational Logic Design Part 2 Combinational Logic Charles Kime & Thomas Kaminski 28 Pearson Education, Inc. (Hyperlinks are active in View Show mode)

2 Overview Part 2 Combinational Logic Functions and functional blocks Rudimentary logic functions Decoding using Decoders Implementing Combinational Functions with Decoders Encoding using Encoders Selecting using Multiplexers Implementing Combinational Functions with Multiplexers Chapter 3 2

3 Functions and Functional Blocks The functions considered are those found to be very useful in design Corresponding to each of the functions is a combinational circuit implementation called a functional block. In the past, functional blocks were packaged as small-scale-integrated (SSI), medium-scale integrated (MSI), and large-scale-integrated (LSI) circuits. Today, they are often simply implemented within a very-large-scale-integrated (VLSI) circuit. Chapter 3 3

4 Rudimentary Logic Functions Functions of a single variable X Can be used on the inputs to functional blocks to implement other than the block s intended function TABLE 4- Functions of One Variable X F = F = X F = X F = V CC or V DD F 5 F 5 X (c) F 5 X F 5 F 5 X F 5 X (a) (b) (d) Chapter 3 4

5 Multiple-bit Rudimentary Functions Multi-bit Examples: A F 3 F 2 F A F (a) A A wide line is used to represent a bus which is a vector signal A In (b) of the example, F = (F 3, F 2, F, F ) is a bus. The bus can be split into individual bits as shown in (b) Sets of bits can be split from the bus as shown in (c) for bits 2 and of F. (b) 4 3,: 3 F F(3), F(:) (d) The sets of bits need not be continuous as shown in (d) for bits 3,, and of F. F 4 2 2: F F(2:) (c) Chapter 3 5

6 Enabling Function Enabling permits an input signal to pass through to an output Disabling blocks an input signal from passing through to an output, replacing it with a fixed value The value on the output when it is disable can be Hi-Z (as for three-state buffers and X transmission gates),, or F When disabled, output When disabled, output See Enabling App in text EN EN X (a) F (b) Chapter 3 6

7 Abilitazione Ix : interruttori S:accensione L:luci R:radio W:finestrini Segnali di controllo Chapter 3 7

8 Abilitazione IS Chapter 3 8

9 Decoding Decoding - the conversion of an n-bit input code to an m-bit output code with n m 2 n such that each valid code word produces a unique output code Circuits that perform decoding are called decoders Here, functional blocks for decoding are called n-to-m line decoders, where m 2 n, and generate 2 n (or fewer) minterms for the n input variables Chapter 3 9

10 Decoder Examples -to-2-line Decoder n=;m=2 2-to-4-Line Decoder A A A D D D 2 D 3 A D 5 A A D 5 A A (a) Note that the 2-4-line made up of 2 -to-2- line decoders and 4 AND gates. (b) D 2 5 A A D 3 5 A A Chapter 3

11 Decoder Expansion General procedure given in book for any decoder with n inputs and 2 n outputs. This procedure builds a decoder backward from the outputs. The output AND gates are driven by two decoders with their numbers of inputs either equal or differing by. These decoders are then designed using the same procedure until 2-to--line decoders are reached. The procedure can be modified to apply to decoders with the number of outputs 2 n Chapter 3

12 Decoder Expansion - Example 3-to-8-line decoder Number of output ANDs = 8 Number of inputs to decoders driving output ANDs = 3 Closest possible split to equal 2-to-4-line decoder -to-2-line decoder 2-to-4-line decoder Number of output ANDs = 4 Number of inputs to decoders driving output ANDs = 2 Closest possible split to equal Two -to-2-line decoders See next slide for result Chapter 3 2

13 Decoder Expansion - Example Costo G = 6+8=24 ; Gn=27 invece di G= 27 ; Gn=3 Chapter 3 3

14 Decoder Expansion Espansione di un line-decoder n-m con m=2 n Si pone k=n ( n ingressi) Se k è pari si utilizzano m porte AND a due ingressi pilotate da due decoder r-2 r con r= k/2 Se k è dispari si utilizzano m porte AND a due ingressi pilotate dai decoder p-2 p con p = (k+)/2 q-2 q con q= (k-)/2 Reiterare la procedura fino ad ottenere decoder -2 o 2-4 Chapter 3 4

15 Decoder Expansion - Example 2 6-to-64 line decoder Numero di AND = 64 Numero di ingressi AND = 6 Il decoder viene suddiviso in 3-to-8-line decoder 3-to-8-line decoder Costo=6*64=384 ; Gn=39 Number of output AND = 8 Numero di ingressi alle porte AND = 3 ( G = 24 ; Gn = 27) Si suddivide in 2-4 line decoder -2 line decoder Costo: 64 * * ( 8*2 + 4*2 ) = 76 Gn=82 Chapter 3 5

16 Decodifica 6-64 Chapter 3 6

17 Decoder with Enable Chapter 3 7

18 Combinational Logic Implementation - Decoder and OR Gates Implement m functions of n variables with: Sum-of-minterms expressions One n-to-2 n -line decoder m OR gates, one for each output Approach : Find the truth table for the functions Make a connection to the corresponding OR from the corresponding decoder output wherever a appears in the truth table Approach 2 Find the minterms for each output function OR the minterms together Chapter 3 8

19 Decoder and OR Gates Example Implement the following set of odd parity functions of (A 7, A 6, A 5, A 3 ) P = A 7 + A 5 + A 3 A 7 P 2 = A 7 + A 6 + A 3 A 6 P 4 = A 7 + A 6 + A 5 A 5 A 4 Finding sum of minterms expressions P = Σ m (,2,5,6,8,,2,5) P 2 = Σ m (,3,4,6,8,,3,5) P 4 = Σ m (2,3,4,5,8,9,4,5) Find circuit Is this a good idea? P P 2 P 4 Chapter 3 9

20 Codifica (Encoding) Codifica - opposto della decodifica - la converione di un codice con m-bit in uno a n-bit con n m 2 n in modo tale che ogni parola di codice produce un valore unico di uscita I circuti sono detti codificatori (encoders) Un codificatore ha 2 n (al massimo) linee di input e n lines di uscita che producono il codice inarion di uscita Tipicamente un codificatore converte un codice che contiene un solo bit in un codice binario che tiene conto della posizione dove l appare. Chapter 3 2

21 Codifica 8-3 Chapter 3 2

22 Codifica con priorità Chapter 3 22

23 Ottimizzazione Chapter 3 23

24 Diagramma Logico Chapter 3 24

25 Encoder Example A decimal-to-bcd encoder Inputs: bits corresponding to decimal digits through 9, (D,, D 9 ) Outputs: 4 bits with BCD codes Function: If input bit D i is a, then the output (A 3, A 2, A, A ) is the BCD code for i, The truth table could be formed, but alternatively, the equations for each of the four outputs can be obtained directly. Chapter 3 25

26 Encoder Example (continued) Input D i is a term in equation A j if bit A j is in the binary value for i. Equations: A 3 = D 8 + D 9 A 2 = D 4 + D 5 + D 6 + D 7 A = D 2 + D 3 + D 6 + D 7 A = D + D 3 + D 5 + D 7 + D 9 F = D 6 + D 7 can be extracted from A 2 and A Is there any cost saving? Chapter 3 26

27 Priority Encoder If more than one input value is, then the encoder just designed does not work. One encoder that can accept all possible combinations of input values and produce a meaningful result is a priority encoder. Among the s that appear, it selects the most significant input position (or the least significant input position) containing a and responds with the corresponding binary code for that position. Chapter 3 27

28 Priority Encoder Example Priority encoder with 5 inputs (D 4, D 3, D 2, D, D ) - highest priority to most significant present - Code outputs A2, A, A and V where V indicates at least one present. No. of Minterms/Row D4 D3 Inputs D2 X D X X 6 X X X X Xs in input part of table represent or ; thus table entries correspond to product terms instead of minterms. The column on the left shows that all 32 minterms are present in the product terms in the table D X X X A2 X Outputs A X A X V Chapter 3 28

29 Priority Encoder Example (continued) Could use a K-map to get equations, but can be read directly from table and manually optimized if careful: A 2 = D 4 A = D 4 D 3 + D 4 D 3 D 2 = D 4 F, F = (D 3 + D 2 ) A = D 4 D 3 + D 4 D 3 D 2 D = D 4 (D 3 + D 2 D) V = D 4 + F + D + D Chapter 3 29

30 Selecting Selecting of data or information is a critical function in digital systems and computers Circuits that perform selecting have: A set of information inputs from which the selection is made A single output A set of control lines for making the selection Logic circuits that perform selecting are called multiplexers Selecting can also be done by three-state logic or transmission gates Chapter 3 3

31 Multiplexers Un multiplexer seleziona informazione da una linea in ingresso e instrada l informazione verso l uscita Un tipico multiplexer ha n input di controllo S n,, S detti ingressi di selezione (selection inputs), 2 n ingressi di informazione (information inputs) I 2 n, I, e un uscita Y Un multiplexer può essere progettato per avere m ingressi di informazione con m < 2 n e n input di selezione Chapter 3 3

32 2-to--Line Multiplexer Since 2 = 2, n = La La variable S ha due valori: S = seleziona l input I S = seleziona l input I Equazione: Y = SI + SI circuito: Chapter 3 32

33 2-to--Line Multiplexer (cont.d) Il circuito del multiplexer puo essere decomposto in: -to-2- Decoder 2 circuiti di abilitazione Porta OR con 2 ingressi Per espandere i multiplexer, si combinano i circuiti di abilitazion e le porte OR in un 2 2 AND-OR circuit: -to-2 decoder 2 2 AND-OR In generale, per un 2 n -to--line multiplexer: n-to-2 n decoder 2 n 2 AND-OR Chapter 3 33

34 Example: 4-to--line Multiplexer 2-to-2 2 -line decoder AND-OR Chapter 3 34

35 Multiplexer 64- Chapter 3 35

36 Espansione di Multiplexer Seleziona vettori di bits invece di bits Usa copie multiple of 2 n 2 AND-OR in parallelo Example: 4-to--line quad multiplexer Chapter 3 36

37 Implementazioni con 3 state buffer Three-state logic in place of AND-OR Gate input cost = 4 compared to 22 for gate implementation Chapter 3 37

38 Implementazione di funzioni logiche con Mux () Si implementano m funzioni di n variabili con: Somma di mintermini Un 2 n -to--line multiplexer a m uscite Design: Si definisce la tavola di verità delle funzioni. In base all ordine con cui appaiono nella tavola di verità: Si applicano le variabili di input della funzione agli ingressi di selezione del multiplexer S n,, S Si etichettano le uscite del multiplexer con le variabili delle funzioni Si attribuiscono i valori della tabella di verità delle funzioni agli ingressi di informazione I 2 n -, I (per don t cares, si applica o indifferentemente) Chapter 3 38

39 Example: Gray to Binary Code Design a circuit to convert a 3-bit Gray code to a binary code The formulation gives the truth table on the right It is obvious from this table that X = C and the Y and Z are more complex Gray A B C Binary x y z Chapter 3 39

40 Gray to Binary (continued) Rearrange the table so that the input combinations are in counting order Gray Binary A B C x y z connecting A, B, and C to the multiplexer select inputs Functions y and z can be implemented using a dual 8-to--line multiplexer by: placing y and z on the two multiplexer outputs connecting their respective truth table values to the inputs Chapter 3 4

41 Gray to Binary (continued) A B C D D D2 D3 D4 D5 D6 D7 S2 S S Out 8-to- MUX Y A B C D D D2 D3 D4 D5 D6 D7 S2 S S Out 8-to- MUX Z Note that the multiplexer with fixed inputs is identical to a ROM with 3-bit addresses and 2-bit data! Chapter 3 4

42 Implementazione con Multiplexer - metodo 2 Si implementano m funzioni di n + variabili utilizzando Un multiplexer a m uscite 2 n -to- Un singolo invertitore Design: Si specifica la tavola di verità della funzione. In base alle prime n variabili di input delle funzioni si raggrupanno le righe delle tabelle di verità a coppie Per ogni coppia di righe in base al valore dell uscita si definisce una funzione elementarex il funzione dell ingresso n+ (,, X, X ) Utilizzando le prime n variabili come indice,si impone il valore degli ingressi di informazione alle relative funzioni elementari Si utilizza l invertitore per generare il negato dell ultima variabile X di ingresso ( X ) Chapter 3 42

43 Example: Gray to Binary Code Design a circuit to convert a 3-bit Gray code to a binary code The formulation gives the truth table on the right It is obvious from this table that X = C and the Y and Z are more complex Gray A B C Binary x y z Chapter 3 43

44 Gray to Binary (continued) Rearrange the table so that the input combinations are in counting order, pair rows, and find rudimentary functions Gray A B C Binary x y z Rudimentary Functions of C for y Rudimentary Functions of C for z F = C F = C F = C F = C F = C F = C F = C F = C Chapter 3 44

45 Gray to Binary (continued) Assign the variables and functions to the multiplexer inputs: C D C D C C C C D D2 Out Y C C D D2 Out Z C D3 C D3 A B S S 8-to- MUX A B S S 8-to- MUX Note that this approach (Approach 2) reduces the cost by almost half compared to Approach. This result is no longer ROM-like Extending, a function of more than n variables is decomposed into several sub-functions defined on a subset of the variables. The multiplexer then selects among these sub-functions. Chapter 3 45

46 Chapter 3 46 Circuiti combinatori con Mux C S Z Y X

47 Chapter 3 47 Circuiti combinatori con Mux C S Z Y X

48 Circuiti combinatori con Mux Chapter 3 48

49 Terms of Use All (or portions) of this material 28 by Pearson Education, Inc. Permission is given to incorporate this material or adaptations thereof into classroom presentations and handouts to instructors in courses adopting the latest edition of Logic and Computer Design Fundamentals as the course textbook. These materials or adaptations thereof are not to be sold or otherwise offered for consideration. This Terms of Use slide or page is to be included within the original materials or any adaptations thereof. Chapter 3 49