Processo di Fabbricazione

Transcript

1 Progettazione Microelettronica Processo di Fabbricazione 1

2 Processo CMOS tradizionale 2

3 Un moderno processo CMOS gate-oxide TiSi 2 AlCu Tungsten SiO 2 n+ p-well p-epi poly n-well p+ SiO 2 p+ Processo CMOS a doppio Well isolato con Trincea 3

4 Circuito Progettato V DD V DD M 2 M 4 V in V out V out2 M 1 M 3 4

5 La sua vista a livello layout 5

6 Processo Fotolitografico ossidazione maschera ottica rimozione fotoresist ricopertura fotoresist esposizione stepper passo di processo Typical operations in a single photolithographic cycle (from [Fullman]). sviluppo fotoresist attacco acido lavaggio essiccamento 6

7 Sagomatura SiO2 di campo Si-substrate (a) Silicon base material Si-substrate (b) After oxidation and deposition of negative photoresist Si-substrate (c) Stepper exposure Photoresist SiO 2 UV-light Patterned optical mask Exposed resist Si-substrate Chemical or plasma etch Hardened resist SiO 2 (d) After development and etching of resist, chemical or plasma etch of SiO 2 Si-substrate (e) After etching Si-substrate Hardened resist SiO 2 SiO 2 (f) Final result after removal of resist 7

8 Principali passi processo CMOS Definizione aree attive Attacco e riempimento trincee Implant well regions Deposit and pattern polysilicon layer Implant source and drain regions and substrate contacts Create contact and via windows Deposit and pattern metal layers 8

9 Analisi del processo CMOS p-epi p+ (a) Base material: p+ substrate with p-epi layer p-epi p+ SiN 3 4 SiO 2 (b) After deposition of gate-oxide and sacrificial nitride (acts as a buffer layer) p+ (c) After plasma etch of insulating trenches using the inverse of the active area mask 9

10 CMOS Process Walk-Through SiO 2 (d) After trench filling, CMP planarization, and removal of sacrificial nitride n (e) After n-well and V Tp adjust implants p (f) After p-well and V Tn adjust implants 10

11 CMOS Process Walk-Through poly(silicon) (g) After polysilicon deposition and etch n+ p+ (h) After n+ source/drain and p+source/drain implants. These steps also dope the polysilicon. SiO 2 (i) After deposition of SiO 2 insulator and contact hole etch. 11

12 CMOS Process Walk-Through Al (j) After deposition and patterning of first Al layer. Al SiO 2 (k) After deposition of SiO 2 insulator, etching of via s, deposition and patterning of second layer of Al. 12

13 Advanced Metallization 13

14 Advanced Metallization 14

15 Design Rules Sono l interfaccia tra il progettista e l ingegnere di processo Forniscono le specifiche per la definizione delle maschere di fabbricazione Unità di misura: minima dimensione regole scalabili: lambda rules regole assolute: (micron rules) 15

16 Vista tridimensionale 16

17 Layers di un processo CMOS Layer Well (p,n) Active Area (n+,p+) Select (p+,n+) Polysilicon Metal1 Metal2 Contact To Poly Contact To Diffusion Via Color Yellow Green Green Red Blue Magenta Black Black Black Representation 17

18 Layers processo CMOS 0.25 µm 18

19 Regole di progetto tra Layers Same Potential Different Potential Well 10 0 or 6 9 Polysilicon 2 2 Active Select Contact or Via Hole 2 2 Metal1 Metal

20 Layout di un Transistore Transistor

21 Contatti e Via 2 1 Via Metal to Active Contact 1 Metal to Poly Contact

22 Select Layer Select Substrate Well 22

23 Layout di un Invertitore CMOS GND In V DD A A Out (a) Layout A A p-substrate n Field Oxide n + (b) Cross-Section along A-A p + 23

24 Layout Editor 24

25 Design Rule Checker poly_not_fet to all_diff minimum spacing = 0.14 um. 25

26 Diagrammi a stick V DD In GND 3 1 Out Entità di layout senza dimensioni Solo la topologia è importante Layout finale generato da un programma di compaction Stick diagram di un invertore 26

27 Packaging Specifiche per il contenitore Elettriche: Bassi parametri parassiti Mechanical: Reliable and robust Thermal: Efficient heat removal Economical: Cheap 27

28 Tecniche di Bonding Wire Bonding Substrate Die Pad Lead Frame 28

29 Tape-Automated Bonding (TAB) Sprocket hole Film + Pattern Solder Bump Test pads Lead frame Polymer film Die Substrate (b) Die attachment using solder bumps. (a) Polymer Tape with imprinted wiring pattern. 29

30 Flip-Chip Bonding Die Solder bumps Interconnect layers Substrate 30

31 Interconnessione Package-Scheda (a) Through-Hole Mounting (b) Surface Mount 31

32 Tipi di Package 32

33 Parametri dei package 33

34 Moduli Multi-Chip 34