Industria dei semiconduttori, tecnologie, progettazione: stato attuale e sviluppi futuri

Industria dei semiconduttori, tecnologie, progettazione: stato attuale e sviluppi futuri Ing. Michele Taliercio CR&D - External R.& D. Program Coordinator Crema, 14 Maggio 2001 STMicroelectronics

Industria dei semiconduttori Mercato Tecnologia Progettazione Fabbrica Fattore umano

Industria dei semiconduttori, tecnologie, progettazione: stato attuale e sviluppi futuri 1) Il mercato 2) La tecnologia 3) La progettazione 4) La fabbrica 5) Il fattore umano

Semiconductor market cycles beyond 2000, long term trend $ Billions 1000 2000 : $204B 1990 : $50B 1980 : $10B MARKET CAGR % : 15% over 40 years 15% over last 10 years 7% over last 5 years % Growth 75% 100 +37% 50% 10 1 0 1959 1961 % Growth 2000 market Current Market Trend Line 1963 1965 1967 1969 1971 1973 1975 1977 1979 Source : WSTS, ST 1981 1983 1985 1987 1989 1991 1993 1995 1997 1999 2001 2003 2005 2007 25% 0% -25% 8

NEW MARKET DRIVING FORCES GROWING SEMICONDUCTOR CONTENT IN ELECTRONIC EQUIPMENT 1965 : 2% 1975 : 4% 1985 : 7% 1995 : 20% 2005 : 25% Main Frame Defense Mid-frame Industrial PC Motherboard Communication Portability Connectivity $400B in 2005 Infrastructure Productivity Corporation Productivity 12" $204B Individual Productivity Commodities Bipolar 2" $1.5B 4" $4B Mem, Micro, Asic Cmos 6" $25B 8" $144B System-on-chip Cmos, Mixed Power 1965 1975 1985 1995 2005 15% 16%

Weather Manual on line Rear View Camera 2010 ELECTRONICS IN THE CAR Drive assistance DRIVER INFORMATION SYSTEM GPS Web traffic Camera Messaging BODY Climate Power seats Lighting Door control MOTOR Engine Transmission Regulator Internet/Games Radio/phone TV/DVD DVD changer ENTERTAINMENT Emergency call SAFETY ABS ASR AirBag Power Steering the Car is connected to the World

2010 Electronics on individual Permanent portable electronics : communication (UMTS, ) leisure (games, music, video, ) work (data processing, ) health monitoring Picture : Siemens + Private data identification mobility tools (GPS, )

2010 Generalized e-commerce Home purchases Street purchase Office purchase Mobile purchase Source : Siemens Paying by mobile phone, by calling the number of the machine

The development of microelectronics is at the very heart of economic development Banking systems Research Services Government action Leisure Computers Communications Medical systems Microelectronics Electronics Education Industry Environment Transportation

Size and price reduction for electronic functions Voice recognition 2000 100$ Image compression Voice recognition 2005 10 $ 2010 1 $ Image compression Communication protocol Processing power Communication protocol Processing power

Economic Impact - Value Added An Industry Built On Sand 10 6 Value Added Chain Sand <$1/kg Polysilicon $50/kg 200mm Prime Wafer $1,400/kg 200mm Processed Wafer $25,000/kg Packaged Integrated Circuit $100.000/kg Generating End Equipment Worth $500,000/kg With A Street Value Of More Than $1,000,000/kg That s What Makes Microelectronics So Important MEDEA Forum 99 Slide 8

Industria dei semiconduttori, tecnologie, progettazione: stato attuale e sviluppi futuri 1) Il mercato 2) La tecnologia 3) La progettazione 4) La fabbrica 5) Il fattore umano

History 1897 Discovery of the electron (J. Thomson) 1907 First termoionic valve (L. De Forest) 1948 First transistor (W. Shockley, J. Bardeen, W. Brattain) 1958 Integrated circuit 1962 MOS transistor 1970 1 Kb DRAM memory 1971 4 bit microprocessor... 80s CMOS convergence... 1993 32 bit microprocessor 1995 64 Mb DRAM (16 Mb production) 1997 256 Mb DRAM (64 Mb production) 1999 1 Gb DRAM (256 Mb production) Central R&D Genova, November 10th, 2000

CMOS Integration Trend: Moore s Law Transistors /chip 10G 1G 100M 10M 1M 100K 10K 4 Kb Central R&D 16 Kb Memory (DRAM) 64 Kb 256 Kb 80286 8086 68000 8085 4 Mb 1 Mb 80386 68020 80286 16 Mb 64 Mb PII Pentium 80486,680 Microprocessor 1 Gb 256 Mb R&D - Jan 2000 COMPANY CONFIDENTIAL J.Monnier PIII 4 Gb Power 4 8080 8085 1K 4004 1970 1975 1980 1985 1990 1995 2000 2005

ITRS Roadmap Potential Acceleration 95 97 99 02 05 08 11 500 350 1994 SIA Minimum Feature Size (nm) (DRAM Half-Pitch) 250 180 130 100 70 50 35 ISMT Litho 2000 Plan 1997 SIA Area for Future Acceleration 1998 / 1999 ITRS 25 95 97 99 02 05 08 11 ST 8/31/00 GF 5

Index [log] 10 000 1000 100 1,20 $ / Mbit 1Tbit Complessità (bit-volume) x 4000 10 22cm² Dimensioni del chip x 8 1 0,1 1996 1999 2002 2005 2008 2011 2014 DRAM Prezzo/Mbit 0,66cts/Mbit x 1/200 256Mbit 18 ans 1Gbit 4Gbit 16Gbit 64Gbit 256Gbit 250 180 130 100 70 50 35 1Tbit Complessità in bit Geometrie in nm Fonte: ITRS, MEDEA

The Optical Lithography perspective Determining the limits of today state of the art photolithography 1999 180 nm 2001 150 nm 2003 130 nm 2006 100 nm 2009 70 nm 2012 50 nm MOS & Interconnect SK SK WR WR HWR BH Contact SK WR HWR HWR BH BH Solutions Known Work Required Hard Work Required Black Hole Source: SEMATECH

The Sub Wavelength Gap Lithography Wavelength Silicon Feature Size Copyright 2000 Numerical Technologies, Inc. 08/08/2000 10:12 AM PAGpr600 GG 3

Interconnect Challenges As technology scales, wires, not devices, dominate the delay, power and size of integrated circuits Interconnect trends Technology generation (nm) 180 130 100 metal levels (number) 6-7 7 7-8 max interconnect length (Km) 1.7 3.3 5.0 Copper, instead of Al, and low K dielectric Below 100nm not known solutions to meet performance requirements Design and layout solutions managing signal delay on a local scale are needed Central R&D Genova, November 10th, 2000

VLSI Process Evolution 2 Year acceleration of technology nodes : 70 nm for DRAM and 45 nm for MPU in 2008 (ITRS) Lithography reaching optical limits New front-end / back-end materials needed Interconnect challenge below 100 nm Defect control: exponentially growing difficulty Technology modeling and new simulation tools Central R&D Genova, November 10th, 2000

VLSI Process Evolution Major non incremental changes : SiGe introduction 1999 Copper replacing Aluminum 2000 300 mm transition 2001 SiO 2 evolving to low K dielectric 2002 High K deposited gate dielectric 2003 Gate electrode poly replacement 2007 Non-optical lithography intercept 2007 Central R&D Genova, November 10th, 2000

CMOS Derivatives DIFFERENTIATED PROCESS VARIANTS BY APPLICATION BICMOS! RF(cellular phone)! Fiber Optic IC Analog! Tuner(Set-Top Box) RFCMOS! Bluetooth HFCMOS! Power Management (Cellular phone) Imager! Web Cam SRAM/DRAM! PC peripherals CMOS CORE PROCESS

Non Volatile Memories (NVM) derivatives DIFFERENTIATED PROCESS VARIANTS BY APPLICATION Multilevel Flash embedded! MP3 Flash embedded! Automotive peripherals EEPROM embedded! Smartcard OTP/EPROM embedded! GPS CMOS NVM CORE PROCESS

Transistor, a silicon perspective M1 : W MOS STI 1 µm MOS poly gate length = 0.25 µm, Shallow Trench Isolation Metal 1 and contact

Metal1, a silicon perspective CMOS 0.25 µm, Shallow Trench Isolation, M1 : Metal1

MOS & inteconnections, silicon perspective M6 : Al Via5 : Al M5 : Al Via4 : Al M4 : Al Via3 : W M3 : Al Via2 : W M2 : Al Via1 : W M1 : W Contact : W CMOS 0.25 µm, STI, 5 Metal Layer with CMP, M6 for bump

Interconnect Delay versus Dielectric K for Al and Cu Normalized Delay 1.2 1.0 0.8 0.6 0.4 Al Cu 0.2 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Dielectric K

Industria dei semiconduttori, tecnologie, progettazione: stato attuale e sviluppi futuri 1) Il mercato 2) La tecnologia 3) La progettazione 4) La fabbrica 5) Il fattore umano

Technology platform for System-On-A-Chip Concurrent Engineering Process & options development Pilot line Production UNICAD tools & methods Cores : µp, DSP, RAM, ROM,... Technology Platform System prototype HW - SW codesign & IP reuse Central R&D Time to Market & flexibility Early access for customers to new prototypes R&D - Jan 2000 COMPANY CONFIDENTIAL J.Monnier

Complex VLSI : Challenges Manage the Complexity System-on-chip design Design Reuse HW/SW Co-design Testing System on a Chip Millions of Gates < 0.18 µm Geometries Manage the Performance Critical dimensions Power Physical Design Reliability Central R&D R&D - Jan 2000 COMPANY CONFIDENTIAL J.Monnier

SOC AT THE HEART OF CONFLICTING TRENDS Time-to-market Process roadmap acceleration Consumerization of electronic devices Link FEI Dolby AC3 Denc ST20 MPEG2 Video Complex systems ucs, DSPs HW/SW SW protocol stacks RTOS Digital/Analog IPs On-Chip busses 2 x 3 DAC Deep sub micron effects crosstalk electro migration wire delays mask costs (OPC, PSM)

ACCELERATION OF TIME Years 20 18 16 14 12 10 8 6 4 2 0 B&W TV Color TV VCR TIME TO 10 MILLION UNITS PC GSM STB DVD 1950 1960 1970 1980 1990 2000 2010 In 2010, instant 10 Million Units volumes will be required

SoC Implementation Platform Cell Libraries Link FEI ST20 IP Blocks Design Tools Dolby AC3 Denc 2 x 3 DAC MPEG2 Video Data Management Central R&D Flows Kits & Methods R&D - Jan 2000 COMPANY CONFIDENTIAL J.Monnier

THE DESIGN PRO D UCTIVITY GAP 10000 100000 Logic Transistors per Chip (M) 1000 100 10 1 0.1 0.01 0.001 CAGR 58% CAGR 21% 10000 1000 100 10 1 0.1 0.01 Productivity (K)Trans./Staff-Mo. 1981 1985 1989 1993 1997 2001 2005 2009 1983 1987 1991 1995 1999 2003 2007 Source ITRS roadmap 1999

Process / Design Gap Design Complexity Process Capability (tr. count linear) System Level Entry HW-SW Methodologies + 60% / year IP Reuse + 20% / year RTL-to-Layout Flow Analog & Full-Custom Design 94 95 96 97 98 99 2000 Year Source : ST Central R&D R&D - Jan 2000 COMPANY CONFIDENTIAL J.Monnier

From System Level down to Silicon, the needs Complement the rich, heterogeneous process technology offer with tools/methods supporting it at architecture and system design levels System Level Entry HW-SW Methodologies RTL-to-layout Flow DSP algorithms, Protocols, Control, Real-time, GUI Executable specifications, system validation DO THE RIGHT THING Processors, memories, logic, datapaths, analog, RF, A/D Virtual prototype, Architecture exploration HW/SW co-verification (co-simulation, co-emulation) High performance S/W compilation DO THE THING RIGHT, FAST Logic, analog, DRAM, SRAM, Flash, High-speed, Power DO IT IN ON A SINGLE CHIP! Process capabilities

CONCLUSION :DEEP SU B MICR O N SOC DESIGN PLATFORMS Application Sensors DRAM CORE DSP CLOCK GEN U A R T J T A G I/O (serial) Fast Prototyping System-Level platform STBUS RF RAM ROM Logic efpga SOC core-std. CMOS logic (Bluetooth, PicoRadio) Flash SOC Process SOC Design Platform

Industria dei semiconduttori, tecnologie, progettazione: stato attuale e sviluppi futuri 1) Il mercato 2) La tecnologia 3) La progettazione I Prodotti 4) La fabbrica 5) Il fattore umano

1980 3.5 µm 0.15 M tr/cm2 1 ML / 5 V 100 mm 1994 0.5 µm 1.5 M tr/cm2 3 ML / 3.3 V 200 mm 2001 0.15 µm 15 M tr/cm2 7 ML / 1.5 V 300 mm ( start of prototyping) Central R&D R&D - Jan 2000 COMPANY CONFIDENTIAL J.Monnier

Evolution of Design Methodology CD's (nm) 250 180 130 100 70 50 Standard cells RC for Clocks 97 98 99 00 01 02 03 04 05 06 07 Dig. libraries RC for all nets Signal isolation INTERCONNECT Block reuse Leakage Crosstalk FlipChip RLC parasitics Block protocols Package simul. Power solution New analog des. New tools & methodology Increased design complexity POWER Appli. specif. platform Combined P&R/synth. New device models Gate current Transmission line eff. Soft errors Current switch Substrate coupling RELIABILITY Years Block communication Signal skew New faults models Signal integrity Local thermal variation Interco. skin effects Source barrier effects Quantum effects New BIST... 10/05/01

STPC industrial PC-ON-CHIP System On Chip X86 Core TFT controller 64-bit Graphics Engine 64-bit Memory controller PCMCIA (Cardbus) PCI & ISA controller Keyboard & Mouse controller Serial & parallel port controller... HCMOS6-5L 140 mm² 2.5 M transistors

Link MPEG2 Audio Encoder RGB YUV ST20-TP2 MPEG2 Video Set-top box for DXX (STi5500) (design DPG & PPG) MPEG2 A/V : 1.3 M tr. ST20-TP2 : 2.0 M tr Link, encoder & DACs : 0.7 M tr. process HCMOS6 CMOS 0.35 µm, 5 ML 4.0 M transistors 96 mm2

ST10 HDD controller with Embedded DRAM (Design DPG) 1 Mbit DRAM HCMOS6 : 0.35 µm, 5 ML ST10 microprocessor & 1 Mb DRAM 1.8 M transistors 49 mm2

DSP952 : core, memories & peripherals SPS2 SPS2 SPS2 SPS2 program data 16 bit fixed point DSP : program memory : 32 kword data memory : 16 kword cycle time : 10 ns SPS2 program SPS2 CORE DPR2 PLL peripherals HCMOS7 : 0.25 µm, 5 ML total area : 27 mm2 core area : 1 mm2

ST10F269-16 bit µc with 2 Mbit Flash 0.35 µm, 5 metal levels, 48 mm 2 M5 M4 M3 M2 M1 Logic interconnection scheme M3 M2 M1 Array interconnection scheme 1.72µm² Flash Cell Central R&D April 7th, 2000

64Mbit Multilevel Flash Memory Technology: 0.18um CMOS triple well double poly triple metal Multilevel Concept: 2bit/cell "11" "10" "01" "00" 4 storage levels 64Mbit = 32Mcells V Read Central R&D - Non Volatile Memory Process Development

Industria dei semiconduttori, tecnologie, progettazione: stato attuale e sviluppi futuri 1) Il mercato 2) La tecnologia 3) La progettazione 4) La fabbrica 5) Il fattore umano

ST Agrate Brianza: Centro Tecnologico R2

Processi Processi di lavorazione delle fette di silicio Il processo richiede circa 400 operazioni e un numero molto elevato di controlli Il tempo di ciclo della produzione è di circa 2 mesi L impianto lavora 24 h / giorno per 7 giorni / settimana Le fette finite e collaudate elettricamente vengono inviate agli stabilimenti di assemblaggio per l incapsulatura plastica

Agrate Brianza - R2 : Caratteristiche dell Impianto Area pulita ( clean room ) : 5600 m 2 Ricircolo dell aria 10 X / minuto Pulizia dell aria 10000 volte quella di una camera operatoria Polverosità : classe 0 (< 1 particella da 0.5 micron / m 3 ) Temperatura controllata : 22 +/ - 0.1 C in litografia Umidità relativa : 40 45 %

Agrate Brianza - R2 : Caratteristiche dell Impianto Prodotti chimici, gas ultrapuri e acqua deionizzata Rete per la distribuzione e raccolta di gas e fluidi di processo Più di 20 prodotti chimici ad alta purezza controllati al punto d uso 2 edifici di servizio per la generazione di acqua deionizzata (120 m 3 / h) e prodotti chimici

Industria dei semiconduttori, tecnologie, progettazione: stato attuale e sviluppi futuri 1) Il mercato 2) La tecnologia 3) La progettazione 4) La fabbrica 5) Il fattore umano

Microelectronics is a "Global Human Challenge" The Microelectronics Industry employs around 800 thousand people worldwide In the assumption: Productivity increase of 10-20% per year Replacing turnover of around 5% per year The industry need will be: 100 thousand people per year 60 thousand highly qualified, highly specialized 40 thousand still classified as operators, but high degree of qualification is a must This Human Capital availability can be the major limiting factor to the Microelectronics growth in the year 2000 s, and primarily in the Western world