UNIVERSITA DEGLI STUDI DI PALERMO

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1 UNIVERSITA DEGLI STUDI DI PALERMO FACOLTA DI INGEGNERIA DIPARTIMENTO ENERGIA, INGEGNERIA DELL INFORMAZIONE E MODELLI MATEMATICI CORSO DI LAUREA SPECIALISTICA IN INGEGNERIA ELETTRONICA BIST AWARE DESIGN AND IMPLEMENTATION OF AN INTEGRATED BLOCK FOR A FLASH MEMORY IN 90nm TECHNOLOGY Tesi di laurea di: Ing. GINEUVE ALIERI Relatore: Prof. Ing. COSTANTINO GIACONIA Tutor aziendale: Ing. ANGELO CIMINO ANNO ACCADEMICO 2012/2013

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3 Ringraziamenti Ringrazio il Prof. Ing. Giuseppe Costantino Giaconia, mio relatore universitario, che mi ha dato la possibilità di svolgere questa tesi presso il gruppo Development Center dello stabilimento STMicroelectronics di Palermo. I miei migliori ringraziamenti vanno all Ing. Angelo Cimino, mio tutor aziendale, all Ing. Andrea Veggetti, all Ing. Ignazio Mocciaro, all Ing. Salvatore Imbesi e all Ing. Abhishek Jain che mi hanno assistito dal punto di vista tecnico e professionale con grande competenza. Un sentito ringraziamento al mio amico e compagno di corso, l Ing. Fulvio Caruso per i suoi indispensabili consigli in più di un occasione. Un grazie di cuore a mia Nonna Agata, sostegno incrollabile nella mia vita, a mia Madre Luciana e a mia Sorella Kerima per avermi sopportato in questi anni di studio e lavoro intensivi (non è stato sempre facile). Un grazie particolare ad Antonella ed ai miei amici di sempre Giorgio e Viola, senza di Voi sarebbe stato tutto più difficile. Grazie anche a Te, che sono sicura guarderai da lassù con il Tuo immenso sorriso. 3

4 Abstract One of the most important phases of Flash memory validation is the analogue resources trimming and in particular the present thesis is related to embedded 272KB Flash named M10ULP (Ultra Low Power) implemented with 90nm technology and developed by STMicrolelectronics. This trimming step is currently done within the EWS (Electrical Wafer Sorting) cycle by using an external device, called ATE (Automated Test Equipment). This solution has several disadvantages: Each trimming procedure has its own test program to be adapted to the ATE every time. Trimming strategy changes depending to the test engineer. Low EWS-Flow efficiency. The proposed solution is based on BIST Techniques (Built In Self Test) with onchip measurements done by Macro s Microcontroller (µc) and some dedicated circuits. The advantages of this solution are: A unified program can be used in any environment to do measurements and trimmings. It could easily be delivered to the customer, without any extra efforts. The accuracy is not compromised, all internal errors and offsets are corrected by the microcontroller and the precision is very high (not depending on external equipment). Reduced EWS Flow time. Negligible impact on the Macro area and on the power (For small Memory cuts the impact must be evaluated accordingly to the specifications while on big memory cuts the impact is really negligible). This thesis describes the specification, design, simulation and implementation on silicon (layout) of the proposed solution called Auto_Trimming_Block included in the test chip of the Flash memory 272kB in M10ULP technology. The simulations show results aligned with expectations and in addition the layout has been developed following all the rules and constraints of the technology. 4

5 The present work will end up with evaluation of all expecting advantages of the proposed on-chip solution; this architecture will be included in dedicated testchips for silicon validation (also checking if and how silicon is aligned with CAD data). In case of positive silicon validation results, the presented structure will be proposed to be integrated in the next Flash macro release. 5

6 Table of Contents Abstract...4 Preface...8 Chapter 1: Flash Memory Memories Architecture FGMOS Elementary Cell Flash Memory Structure Memory Operation Read Operation Program Operation Erase Operation Memory Operation Problems Over-Erasing Program Problems Read Problems Chapter 2: Test Techniques Failure Mechanisms and Test Generation Design for Testability Methods Scan Method Built-In-Self-Test (BIST)

7 Chapter 3: Implementation of the Auto_Trimming_Block Architecture of Auto_Trimming_Block The comparator The Ladder_256Level with its Decoder Log_inladder block Ladder_4Level with its Decoder Auto_Trimming_Block Simulation Chapter 4: Layout of the Auto_Trimming_Block Comparator Layout Ladder_256Level and its Decoder Layout Log_inladder Layout Ladder_4Level andits Decoder Layout Auto_Trimming_Block Complete Layout Conclusions...80 Bibliography