Multi processor architecture

Transcript

1 Multi processor architecture A short introduction Grigory Rechistov IntelMIPT lab, MDSP project March 2011

2 Introduction Moving from single CPU systems to multiprocessor ones requires much more eort than it would seem. 1. Topology questions 2. Resource sharing 3. Message passing 4. Platform startup

3 Introduction Moving from single CPU systems to multiprocessor ones requires much more eort than it would seem. 1. Topology questions 2. Resource sharing 3. Message passing 4. Platform startup We don't consider the issues of programming MP systems.

4 3 Processor units hierarchy Package Core #1 Core #2 Thread #1 Thread #1 Thread #2 Thread #2

5 4 What is hyperthreading HT [1] works by duplicating certain sections of the processor those that store the architectural state but not duplicating the main execution resources. RAM L1, L2 Arch state #1 Execution resource #1 Arch state #2 Execution resource #2

6 HT: pros and cons Pros: I Utilizes resources that might otherwise stall. I Up to 30% faster than same CPU without HT. I Uses only 5% more of die area. Cons: I Is not true multicore. I Requires OS awareness to correctly utilize HT. I Poses security vulnerability [2].

7 6 Multicore systems and their caches Type of cache sharing depends on the system: it can be L2 that is shared etc.

8 Types of coherence protocols 1. Directory-based: the data being shared is placed in a common directory that maintains the coherence between caches. The directory acts as a lter through which the processor must ask permission to load an entry from the primary memory to its cache. When an entry is changed the directory either updates or invalidates the other caches with that entry. 2. Snooping: individual caches monitor address lines for accesses to memory locations that they have cached. When a write operation is observed to a location that a cache has a copy of, the cache controller invalidates its own copy of the snooped memory location.

9 Caches coherency protocol example: MESI 8

10 Other protocols I MOSI protocol I MOESI protocol I MESIF protocol I MERSI protocol

11 SMP Stands for Symmetric Multi Processing I Identical processing units I Single shared memory I Single bus, mesh interconnections Problem: scalability (systems with > 8 units will have performance problems)

12 NUMA Stands for Non Uniform Memory Access Memory access time depends on the memory location relative to a processor. Under NUMA, a processor can access its own local memory faster than non-local memory, I Highly scalable I Requires special coherency protocols I Requires OS support AMD: Opteron (HyperTransport) Intel: Intel Core i7-9xx (QPI)

13 APIC, IO-APIC Stands for Advanced Programmable Interrupt Controller Programmable interrupt controller (PIC) is a device that is used to combine several sources of interrupt onto one or more CPU lines, while allowing priority levels to be assigned to its interrupt outputs.

14 Boot process 1. The BSP 1 executes the BIOS's boot-strap code to congure the APIC environment, sets up system-wide data structures, starts and initializes the AP 2 s. When the BSP and APs are initialized, the BSP then begins executing the operating-system initialization code. 2. Following a power-up or reset, the APs complete a minimal self-conguration, then wait for a startup signal (a SIPI message) from the BSP processor. Upon receiving a SIPI message, an AP executes the BIOS AP conguration code, which ends with the AP being placed in halt state. [3] 1 Boot strap processor. 2 Application processor

15 14 More to read ftp://download.intel.com/technology/itj/2002/ volume06issue01/vol6iss1_hyper_threading_ technology.pdf processors/pro/docs/ pdf

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