Exam of DIGITAL ELECTRONICS June 21 st, 2012 Prof. Marco Sampietro

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1 Exam of DIGITAL ELECTRONICS June 21 st, 2012 Prof. Marco Sampietro Student I.D. number NAME Si consideri il circuito digitale combinatorio della figura seguente. La tensione d alimentazione è 5V e la soglia di commutazione delle porte è posta a metà dinamica. Si supponga che su ogni uscita delle porte logiche sia presente una capacità parassita di 0.2pF. (Consider the following circuit. The voltage supply is 5V and the gates threshold is in the middle of its dynamic range. At the output of each logic gate there is a parasitic capacitance of 0.2pF) A B Y C a) Determinare la tabella della verità del circuito. (Write the truth table of the circuit) - 1 -

2 b) Considerando gli ingressi A e B a massa e l ingresso C connesso ad un clock di frequenza 500MHz, calcolare la potenza dinamica dissipata dal circuito. (Consider A and B connected to ground and C connected to a clock at f=500mhz. Calculate the dynamic power dissipated by the circuit). P dyn = c) Sintetizzare un circuito più semplice del precedente che realizzi la stessa tabella della verità ed immune da hazards. Calcolare su questo nuovo circuito la potenza dinamica dissipata nelle condizioni del punto b). (Find a simpler circuit with the same truth table and with no hazards and calculate its dynamic power dissipation in the same condition as in b)) - 2 -

3 Suppose to have a ROM (Read Only Memory) made of 2 10 words of 64 bits each. Suppose the memory is, on the average, occupied by 0 and 1 in equal numbers. The available CMOS technology is the following: p =400 cm 2 /V s, n =1200 cm 2 /V s, C ox =1000 nf/cm 2, V T =0.4V, L min =90nm. Each 0 in the memory is made with the following circuit having W p =W n =L min. +1.9V W.L. B.L. a) Find the maximum current in the pmosfet and in the nmosfet. Draw the characteristic curves of the transistors and indicate the working point of the transistors when the memory cell is a 0 and when the memory cell is a 1. I pmos max = I nmos max = - 3 -

4 b) Supponendo che C DG =C G /3, calcolare la capacità totale di carico di ogni Bit-line (Find the total load capacitance of each Bit-line, supposing that the Drain-to-Gate capacitance is equal to 1/3 of the Gate capacitance of the transistor) C bit-line = c) Find the delay time between the moment you address the word line (W.L.) and the moment you have updated the output bits. t delay = - 4 -

5 d) Find the static power dissipated by the full memory during its operation P st ROM = e) Find the additional dynamic power dissipated by the full memory when it is operated at an addressing frequency of 100MHz. P dyn ROM = f) Find the total power dissipated by the memory when operated at 1GHz. P tot ROM = - 5 -

6 ADC system design Suppose you have an acquisition system as in the following : V G pmosfet +3V V H ADC V in V G nmosfet CH=80fF -3V a) Find the maximum amplitude of a sinusoidal input signal V in (t) that can be sampled by this system and the minimum number of bits N min of the ADC in order to have a resolution better than 2mV. V in max = N min ADC = b) By taking the resistance R DSon of the MOSFET switch well approximated in its value by 1 R DSon, find the value of R DSon when it is operated with V G =5V in the case k(vgs VT ) k=1ma/v 2 and V T =0.6V for both nmosfet and pmosfet. Calculate the value of R DSon as an average of the value obtained when the input signal is minimum and when it is maximum

7 R DSon = c) Find the maximum sampling frequency of the system, supposing that the ADC is infinitely fast in its convertion. f samp = - 7 -