Mauro Caule mat. 118381 Fabrizio Castellano mat. 122390 Luigi Fasano mat. 120730 ELETTRONICA DELLE TELECOMUNICAZIONI II ESERCITAZIONE DI LABORATORIO N.2 CODICE VHDL Torino, 16/05/2005 ENTITY sipo IS data_in: IN END sipo ; STD_LOGIC; clock_ad : IN STD_LOGIC; data_out : OUT STD_LOGIC_VECTOR(7 downto 0 reset : IN STD_LOGIC; clock_out : IN STD_LOGIC ARCHITECTURE behavioral OF sipo IS SIGNAL temp : STD_LOGIC_VECTOR(7 downto 0 process (clock_out) if clock_out= '1' and clock_out'event then data_out<=temp; process (clock_ad, reset) if reset= '0' then temp <= (others=> '0' data_out <= (others=> '0' elsif clock_ad = '1' and clock_ad'event then temp(0) <= data_in; for i in 1 to 7 loop temp(i) <= temp(i-1 end loop; END behavioral;
ENTITY div_freq IS clk_in : IN STD_LOGIC; clk_out : OUT STD_LOGIC; cs_out : OUT STD_LOGIC END div_freq ; -- Library declaration ARCHITECTURE behavioral OF div_freq IS PROCESS(clk_in) CONSTANT N : integer := 50; VARIABLE cnt : integer range 0 to N; VARIABLE cnt2 : integer range 0 to 16*N; VARIABLE status : std_logic := '0'; VARIABLE clk_cs : std_logic := '0'; cs_out <= clk_cs; clk_out <= status; if (clk_in'event and clk_in = '1') then cnt2:=cnt2+1; cnt:=cnt+1; if (cnt=n) then cnt:=0; if (status='0') then status:='1'; else status:='0'; if (cnt2=n*16) then cnt2:=0; if (clk_cs='0') then clk_cs:='1'; else clk_cs:='0'; END behavioral;
use ieee.std_logic_unsigned.all; ENTITY fwrectifier IS --clk : IN STD_LOGIC; --clock fw_hw : IN STD_LOGIC; -- 1= full wave, 0 half wave data_in : IN STD_LOGIC_VECTOR(7 downto 0 -- ingresso data_out : OUT STD_LOGIC_VECTOR(7 downto 0 --uscita level: IN STD_LOGIC_VECTOR(7 downto 0) -- livello centrale END fwrectifier; ARCHITECTURE struct OF fwrectifier IS signal s_out : STD_LOGIC_VECTOR(7 downto 0 process(data_in,level) if data_in > level then s_out <= data_in; elsif fw_hw = '0' then s_out <= level; else s_out <= level + level - data_in; data_out <= s_out; END struct;
use ieee.std_logic_unsigned.all; ENTITY volt_dig IS clk_io : IN STD_LOGIC; data_adc : IN STD_LOGIC; cs : OUT STD_LOGIC; io_clock : OUT STD_LOGIC; data1 : OUT STD_LOGIC_VECTOR(7 downto 0 data2 : OUT STD_LOGIC_VECTOR(7 downto 0 rst : IN STD_LOGIC; rect_in: IN std_logic END volt_dig ; ARCHITECTURE struct OF volt_dig IS signal t_osc : std_logic; signal t_data : std_logic; signal t_cs : std_logic; signal t_clk_ad : std_logic; signal t_data_out: STD_LOGIC_VECTOR(7 downto 0 signal t_sipo_out: STD_LOGIC_VECTOR(7 downto 0 signal t_reset: std_logic; signal t_1: std_logic; signal t_128: std_logic_vector(7 downto 0 -- Component declarations COMPONENT div_freq clk_in : IN STD_LOGIC; clk_out : OUT STD_LOGIC; cs_out : OUT STD_LOGIC END COMPONENT; COMPONENT sipo data_in: IN STD_LOGIC; clock_ad : IN STD_LOGIC; data_out : OUT STD_LOGIC_VECTOR(7 downto 0 reset : IN STD_LOGIC; clock_out : IN STD_LOGIC
END COMPONENT; COMPONENT fwrectifier --clk : IN STD_LOGIC; --clock fw_hw : IN STD_LOGIC; -- 1= full wave, 0 half wave data_in : IN STD_LOGIC_VECTOR(7 downto 0 -- ingresso data_out : OUT STD_LOGIC_VECTOR(7 downto 0 --uscita level: IN STD_LOGIC_VECTOR(7 downto 0) -- livello centrale END COMPONENT; t_1 <= '1'; t_128 <= "10000000"; t_reset <= '1'; t_osc <= clk_io; t_data <= data_adc; --t_reset <= rst; data1 <= t_data_out; data2 <= t_data_out; -- uscite -- uscite -- Component instantiation freq_div0:div_freq PORT MAP ( clk_in => t_osc, clk_out => t_clk_ad, cs_out => t_cs si_po:sipo PORT MAP ( data_in => t_data, clock_ad => t_clk_ad, data_out => t_sipo_out, reset => t_reset, clock_out => t_cs rect:fwrectifier PORT MAP( --clk => t_cs, --clock fw_hw => rect_in, -- 1= full wave, 0 half wave data_in => t_sipo_out,-- ingresso data_out => t_data_out, --uscita level => t_128 -- livello centrale
cs <= t_cs; io_clock <= t_clk_ad; END struct;