Multi-StandardLow-Power Base-Band Digital Receiver, Enhancedfor HSDPA

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1 Diss. ETH No Multi-StandardLow-Power Base-Band Digital Receiver, Enhancedfor HSDPA A dissertation submitted to the SWISS FEDERAL INSTITUTEOF TECHNOLOGY ZÜRICH for the degree of Doctor of Technical Sciences presented by CHIARA MARTELLI M.S., Alma Mater Studiorum University of Bologna, Italy born Citizen of Italy accepted on the recommendation of Prof. Dr. Q. Huang, examiner Prof. Dr. H. Bölcskei, co-examiner 2006

2 Abstract A digital front-endfor multi-standard GSM/W-CDMA/WLAN(Global System for Mobile Communications, Wide-Band Code Division Mul tiple Access, Wireless Local Area Network) wireless Communications comprises a cascade of configurablesinc-cic (Cascaded Integrator- Comb) Filter, half-band and FIR (Finite Impulse Response) filter stages as well as variable gain and RSSI (Received Signal Strength Indication) [53]. A distributed AGC (Automatic Gain Control) is driven by an externaldsp (Digital Signal Processor), on the basis of the signal power estimations led along the data path. That existing system has been adapted to support I and Q Chan nels communication and to meet the requirements imposed by the newly designed signal processing part for UMTS (UniversalMobile TelecommunicationsSystem) new generation Standard. Frequency offset estimation and compensation has been designed on two stages to remedy frequency offsets up to ±40kHz. In other words the system allows crystal precision downto 20PPM, insteadof 0.1PPM, as the Standards require. Synchronization to the power control period (or slot) boundaries and to the frame boundaries has been carried out, taking particular care to the area occupation of this block. Cell Selection has been modeledoff-chip on the basis of Turbo and/or Viterbi decoders also off-chip. the specific This ensures the correct selection of spreading code to be used during connections to the UE XI

3 Abstract A digitalfront-endfor multi-standard GSM/W-CDMA/WLAN(Global Systemfor Mobile Communications, Wide-BandCode Division Mul tiple Access, Wireless Local Area Network) wireless Communications comprises a cascade of configurablesinc-cic (Cascaded Integrator- Comb) Filter, half-band and FIR (Finite Impulse Response) filter stages as well as variable gain and RSSI (Received Signal Strength Indication) [53]. A distributed AGC (Automatic Gain Control) is driven by an external DSP (Digital Signal Processor), on the basis of the signal power estimationsled along the data path. That existing system has been adapted to support I and Q Chan nels communication and to meet the requirements imposed by the newly designed signal processing part for UMTS (UniversalMobile TelecommunicationsSystem) new generation Standard. Frequency offset estimation and compensation has been designed on two stages to remedy frequency offsets up to ±40kHz. In other words the system allowscrystalprecision downto 20PPM, insteadof 0.1PPM, as the Standards require. Synchronization to the power control period (or slot) boundaries and to the frame boundaries has been carried out, taking particular care to the area occupation of this block. Cell Selection has been modeled off-chip on the basis of Turbo and/or Viterbi decoders also off-chip. the specific This ensures the correct selection of spreading code to be used during connections to the UE XI

4 xii ABSTRACT (User Equipment). A Rake receiver has been designed to ensure one user decodingand to support the different user code aggregation required in HSDPA (High Speed DownlinkPacket Access) mode. Maximum Ratio Combining (MRC) guarantees better Performances in terms of Symbol stream bit error rate. Particularcare has been exercised to lower power consumption: mas sive clock gating has been manually introduced in the architecture to minimize the switching power activity. Additionally, temporarily unused blocks are automatically powered down. Along the digital flow, low-vt cells have been used only where needed to meet the timing constraints: the very reduced number of low-vt cells assures minimizationof leakage power. The design has been first verified on a Xilinx Virtex-II 6000 FPGA has been afterwards integrated (Field Programmable Gate Array), it in 0.13/im CMOS technology at the Institute of Integrated Circuits (IIS) at the Swiss Federal Institute of Technology (ETH) in Zürich (Switzerland). The system model has been constantly checked and proven in a Soft ware environment, as well as on an FPGA and an ASIC (Application Specific Integrated Circuit). Advantages and disadvantages related to those different contextshave been highlightedthroughoutthe way, and the still strong supremacy of integratedcircuits has been evinced over non-custom architectures.

5 Sommario Un front-end digitale multi-standard GSM, W-CDMA,WLAN (Glo bal System for Mobile Communications, Wide-Band Code Division Multiple Access, Wireless Local Area Network) per comunicazioni di tipo wireless e costituito di un primo filtro programmabile di ti po SINC-CIC, seguito da due stadi di tipo passa-basso (di tipo Half Band Filter, o HBF) e da un filtro di adattamento (di tipo Finite Impulse Response, o FIR) [53]. Cinque stadi di tipo RSSI (Received Signal Strength Indication) sono distribuiti lungo il percorso dei dati ed impostano i valori di guadagnoda applicareal segnale. Tale valore e calcolato da un DSP (Digital Signal Processor) esterno che riceve le informazioni dagli RSSI suddetti. II sistema, che era giä stato realizzato per un canale, e stato adattato per ospitare le parti reale ed immaginaria del segnale e per soddisfare le specifiche imposte dal processore di segnale a modulazione UMTS posto a valle, realizzato per questa tesi. La stima e la correzionedella differenza in frequenza tra gli oscillatori del trasmettitore e ricevitore sono state realizzate tramite due stadi separati, che permettono al sistema di sopportare errori di frequenza fino a ±40kHz; in altre parole questo sistema permette di usare quarzi con precisione di soli 20PPM, anziehe quelli con precisione 0.1PPM, come richiesto dalle specificheumts (UniversalMobile Telecommu nications System). La sincronizzazioneai margini di slot e frame del segnale UMTS e resa possible attraverso l'uso di un filtro di adattamento per il quäle xni

6 xiv SOMMARIO si e prestata particolare attenzione alla minimizzazionedell'area occupata sul chip. La Cell Selection UMTS e stata realizzata fuori dal chip, sulla base di decodificatori Turbo e/o Viterbi, a loro volta implementati su un microprocessore esterno. Questo per selezionare lo specifico spreding code da utilizzaredurante ogni successiva trasmissione. E' stato progettato un opportuno Rake receiver per consentire la corretta decodifica del canale utente, o, in caso di modulazione HSDPA (High Speed Downlink Packet Access), rispettivamente dei 5, 10, o 15 canali utenti sumultanei. A valle del Rake receiver, un MRC (Ma ximum Ratio Combining) permette di ottenere migliori risultati in termini di Bit Error Rate (BER). Particolare attenzione e stata prestata nel ridurre al massimo il consumo di potenza. II clock gating e stato introdotto massivamente in modo da ridurre il piü possibile l'attivitä dinaminca; i blocchitemporaneamente non utilizzati vengono spenti completamente, mantenendo statico il segnale di clock. Oltre a questo, si e cercato di limitare l'uso di celle a bassa Vt ai soli blocchi critici dal punto di vista delle temporizzazioni;altrimenti sono state utilizzate celle ad alta Vt per minimizzarele correnti di perdita. II sistema e stato prima verificato su una FPGA (Field Program mable Gate Array, Xilinx Virtex-II 6000) e poi integrato in tecnologia 0.13/zm CMOS al Dipartimentodi Circuiti Integrati (IIS), appartenente alltstituto Federaledi Tecnologia (ETH) di Zurigo (Svizzera). II modello del sistema e stato provato mediante simulazione Softwaree programmazionedi un DSP, implementazione su FPGA, integrazione del chip. In questo modo si sono apprezzati i vantaggi e gli svantaggi dei tre contesti menzionati. La supremaziadel circuito integrato di ti po custom si e affermata sulle altre due implementazionipiü generiche e riprogrammabili.