Reti Logiche A. FSM in VHDL

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Italo Longo
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1 Reti Logiche A FSM in VHDL Gianluca Palermo Politecnico di Milano Dipartimento di Elettronica e Informazione gpalermo@fusberta.elet.polimi.it Macchina a Stati Finiti (FSM) Tipo Moore IN NEXT STATE LOGIC RST NEXT STATE CURRENT STATE OUTPUT LOGIC OUT Esempio: Macchina di Moore a due stati S/ S/ RST 2

2 Esempio: Macchina di Moore (3 process) entity moore is port( clk,rst,input: in bit; output:out bit); end moore; architecture ex of moore is type state_type is (S,S); signal current_state, next_state: state_type; ff: process (clk,rst) if rst = then state <= S; elsif (clk'event and clk = '') then current_state <= next_state; end process ff; st: process (current_state) case current_state is when S => if input= then next_state <= S; next_state <= S; 3 Esempio: Macchina di Moore (3 process) when S => if input= then next_state <= S; next_state <= S; end process st; out_p: process (current_state) case current_state is when S => output <= ; when S => output <= ; end process out_p; end ex; 4

3 Esempio: Macchina di Moore (2 process) entity moore is port( clk, rst, input: in bit; output: out bit); end moore; architecture ex2 of moore is type state_type is (S,S); signal current_state, next_state: state_type; ff: process (clk,rst) if rst = then state <= S; elsif (clk'event and clk = '') then current_state <= next_state; end process ff; st: process (current_state, input) case current_state is when S => output <= ; if input= then next_state <= S; next_state <= S; 5 Esempio: Macchina di Moore (2 process) when S => output <= ; if input= then next_state <= S; next_state <= S; end process st; end ex2; 6

4 Esempio: FSM_ Tipo Moore C_IN [ ] FSM_ RST Y_OUT [ ],- -,- -,- RST ST Y_OUT ST ST ST 7 Codice Sorgente di FSM_ Tipo Moore entity FSM_ is port ( RST, : in bit; C_IN : in bit_vector ( to ); Y_OUT : out bit_vector ( to )); end FSM2; architecture MOORE of FSM_ is type STATE_TYPE is ( ST,,, ); signal CURRENT_STATE, NEXT_STATE : STATE_TYPE; Processo sequenziale SEQ: process (, RST) if RST = '' then CURRENT_STATE <= ST; elsif ('event and = '') then CURRENT_STATE <= NEXT_STATE; end process SEQ; 8

5 Codice Sorgente di FSM_ - Tipo Moore (cont.) Processo Combinatorio per Next State Logic COMB: process (current_state,c_in) case CURRENT_STATE is when ST => if (C_IN="" or C_IN="" or C_IN="") then NEXT_STATE <= ; NEXT_STATE <= ST; when => if (C_IN="" or C_IN="" or C_IN="") then NEXT_STATE <= ; NEXT_STATE <= ST; when => if (C_IN="" or C_IN="" or C_IN="") then NEXT_STATE <= ; NEXT_STATE <= ; 9 Codice Sorgente di FSM_ - Tipo Moore (cont.) when => if ( C_IN="" or C_IN="") then NEXT_STATE <= ; NEXT_STATE <= ; end process COMB; Processo Combinatorio per Output Logic OUT_LOGIC: process (CURRENT_STATE) case CURRENT_STATE is when ST => Y_OUT <= ""; when => Y_OUT <= ""; when => Y_OUT <= ""; when => Y_OUT <= ""; end process OUT_LOGIC; end MOORE;

6 Esempio: FSM_A Tipo Moore X FSM_A Z S S S3 X = X = Z S S S S S3 S3 S3 S Codice Sorgente di FSM_A Tipo Moore entity FSM_A is port( X, : in bit; Z: out bit); end FSM_A; architecture MOORE of FSM_A is type STATE_TYPE is ( S, S,, S3); signal CURRENT_STATE, NEXT_STATE : STATE_TYPE; SEQ: process wait until('event and = ''); CURRENT_STATE <= NEXT_STATE; end process SEQ; COMB_OUT:process (CURRENT_STATE, X) case CURRENT_STATE is when S => Z <= ; if (X = ) then NEXT_STATE <= S; NEXT_STATE <= ; 2

7 Codice Sorgente di FSM_A Tipo Moore (cont.) when S => Z <= ; if (X = ) then NEXT_STATE <= S; NEXT_STATE <= ; when => Z <= ; if (X = ) then NEXT_STATE <= ; NEXT_STATE <= S3; when S3 => Z <= ; if (X = ) then NEXT_STATE <= S3; NEXT_STATE <= S; end process COMB_OUT; end MOORE; 3 Macchina a Stati Finiti (FSM) Tipo Mealy IN NEXT STATE LOGIC and OUTPUT LOGIC OUT CURRENT_STATE NEXT_STATE RST 4

8 Esempio: FSM_B Tipo Mealy X STA / STC / Z / / / / STB / STD / X = X = STA STB / STC / STB STB / STD / STC STC / STD / STD STD / STA / 5 Codice Sorgente di FSM_B Tipo Mealy entity FSM_B is port ( X, : in bit; Z: out bit); end FSM_B; architecture MEALY of FSM_B is type STATE_TYPE is ( STA, STB, STC, STD); signal CURRENT_STATE, NEXT_STATE : STATE_TYPE; SEQ: process wait until('event and = ''); CURRENT_STATE <= NEXT_STATE; end process SEQ; COMB_OUT:process (CURRENT_STATE, X) case CURRENT_STATE is when STA => if (X = ) then Z <= ; NEXT_STATE <= STB; Z <= ; NEXT_STATE <= STC; 6

9 Codice Sorgente di FSM_B Tipo Mealy (cont.) when STB => if (X = ) then Z <= ; NEXT_STATE <= STB; Z <= ; NEXT_STATE <= STD; when STC => if (X = ) then Z <= ; NEXT_STATE <= STC; Z <= ; NEXT_STATE <= STD; when STD => if (X = ) then Z <= ; NEXT_STATE <= STD; Z <= ; NEXT_STATE <= STA; end process COMB_OUT; end MEALY; 7

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