La Microelettronica e il suo impatto invasivo sullo sviluppo industriale

Transcript

1 La e il suo impatto invasivo sullo sviluppo industriale Fausto Fantini Dipartimento di Ingegneria dell Informazione Università degli Studi di Modena e Reggio Emilia Scuola Normale Superiore di Pisa 49 Corso di Orientamento Universitario 2006 Sabato 2 Settembre

2 Dov è la? INFORMATICA TELECOMUNICAZIONI AUTOMAZIONE CONSUMER AUTOVEICOLO 2

3 Cos è la? TECNOLOGIE DISPOSITIVI CIRCUITI SISTEMI 3

4 Segnali elettrici Una qualunque grandezza fisica che possa venire impiegata per scambiare informazioni è un segnale. L elettronica si occupa dell elaborazione dei segnali elettrici. 4

5 Segnali elettrici S(t) Segnali analogici S(t) può assumere tutti i valori nell intervallo di interesse t 5

6 Segnali elettrici Segnali numerici (o digitali). Possono assumere solo un numero finito di valori. Quando i valori ammessi sono solo 2, si dicono binari. Si riducono i rischi di errori. 6

7 S(t) t Analogico S(t) S 2 S 1 S 0 S -1 t 1 t 2 t 3 t t 4 5 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t Numerico S -2 S(t) S 1 S 0 Binario t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 7

8 Sistemi elettronici Insieme di componenti ed elementi circuitali che, connessi tra loro in modo opportuno, risolvono problemi di rilevamento, controllo ed elaborazione di grandezze fisiche. 8

9 Schema generale SENSORE ATTUATORE ACQUISIZIONE ELABORAZIONE EMISSIONE CONTROLLO 9

10 Sistema elettronico Acquisizione: introduce nel sistema le grandezze da elaborare. Elaborazione: elabora il segnale. Emissione: fornisce all uscita del sistema le grandezze risultanti. Controllo: garantisce il rispetto dei parametri di riferimento stabiliti. 10

11 Applicazioni tradizionali dell elettronica elettronica Telecomunicazioni Informatica 11

12 Componenti elettronici Amplificatori Interruttori controllati 12

13 The First Computer The Babbage Difference Engine (1832) 25,000 parts cost: 17,470 13

14 L elettrone Carica: 1,6 x C Massa: 9,11 x Kg Numero di elettroni per C: 6 x pA = C/s 6 milioni di elettroni al secondo 14

15 Componenti elettronici Tubi a vuoto ( valvole ): diodo, triodo, tetrodo, pentodo (Relè) La loro applicazione è stata limitata da: Ingombro e peso Consumo Affidabilità 15

16 Tubo a vuoto 16

17 ENIAC - The first electronic computer (1946) 17

18 The Transistor Revolution First Ge transistor Bell Labs,

19 Proprietà dei semiconduttori Silicio, Germanio, semiconduttori composti (GaAs, InP, SiC, GaN, SiGe ) σ = (Ω cm) -1 σ cresce fortemente con la temperatura σ varia fortemente con la presenza di impurezze (droganti) Portatori di carica negativi (elettroni) e positivi (lacune) 19

20 The Diode B Al A SiO 2 p n Cross-section of pn-junction in an IC process A p n B One-dimensional representation Al A B diode symbol 20

21 Diode Current 21

22 STRUTTURA E TERMINOLOGIA Un transistore bipolare a giunzione (BJT) npn è costituito da una regione di semiconduttore di tipo p (detta base) interposta tra due regioni di tipo n (dette emettitore e collettore). In un BJT sono pertanto presenti due giunzioni p-n: la giunzione baseemettitore (B-E) e la giunzione base-collettore (B-C). E l interazione tra queste due giunzioni che rende il BJT utilizzabile come amplificatore e come interruttore. 22

23 Fattori determinanti il successo delle microelettronica Miniaturizzazione (CI) Velocità Consumo Costo 23

24 The First Integrated Circuits Si Bipolar logic 1960 s ECL 3-input Gate Motorola

25 Tecnologia del Silicio Il Germanio non funziona ad alte temperature (>70 C). La tecnologia planare del Silicio è stata determinante per la scelta del materiale semiconduttore per l industria microelettronica. 25

26 Patterning of SiO2 Si-substrate (a) Silicon base material Si-substrate (b) After oxidation and deposition of negative photoresist Si-substrate (c) Stepper exposure Photoresist SiO 2 UV-light Patterned optical mask Exposed resist Si-substrate Si-substrate (e) After etching Si-substrate Chemical or plasma etch Hardened resist SiO 2 (d) After development and etching of resist, chemical or plasma etch of SiO 2 Hardened resist SiO 2 SiO 2 (f) Final result after removal of resist 26

27 Photo-Lithographic Process oxidation optical mask photoresist removal (ashing) photoresist coating stepper exposure process step Typical operations in a single photolithographic cycle (from [Fullman]). spin, rinse, dry acid etch photoresist development 27

28 Circuiti Integrati Il transistor bipolare non si presta ad essere integrato in circuiti molto complessi. Viene usato quasi sempre il transistor a effetto di campo, basato sulla struttura MOS (metallo-ossido-semiconduttore). 28

29 The MOS Transistor Polysilicon Aluminum 29

30 Switch Model of NMOS Transistor V GS Gate Source (of carriers) Drain (of carriers) Open (off) (Gate = 0 ) Closed (on) (Gate = 1 ) R on V GS < V T V GS > V T 30

31 Switch Model of PMOS Transistor V GS Gate Source (of carriers) Drain (of carriers) Open (off) (Gate = 1 ) Closed (on) (Gate = 0 ) R on V GS > V DD V T V GS < V DD V T 31

32 The NMOS Transistor Cross Section n areas have been doped with donor ions (arsenic) of concentration N D - electrons are the majority carriers W Source n+ Polysilicon Gate L Gate oxide Drain n+ Field-Oxide (SiO 2 ) p substrate p+ stopper Bulk (Body) p areas have been doped with acceptor ions (boron) of concentration N A - holes are the majority carriers 32

33 Current-Voltage Relations A good ol transistor -4 x 10 6 VGS= 2.5 V 5 4 Resistive Saturation VGS= 2.0 V I D (A) 3 V DS = V GS -V T Quadratic Relationship 2 VGS= 1.5 V 1 VGS= 1.0 V V DS (V) saturation 33

34 Summary of MOSFET Operating Regions Strong Inversion V GS >V T Linear (Resistive) V DS <V DSAT Saturated (Constant Current) V DS V DSAT Weak Inversion (Sub-Threshold) V GS V T Exponential in V GS with linear V DS dependence 34

35 Moore s s Law In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months. He made a prediction that semiconductor technology will double its effectiveness every 18 months 35

36 Moore s s Law LOG2 OF THE NUMBER OF COMPONENTS PER INTEGRATED FUNCTION Electronics, April 19, Fausto EE141 Fantini

37 Moore s s Law 37

38 MOSFET evolution 38

39 Intel 4004 Micro-Processor transistors 1 MHz operation 39

40 Intel Pentium (IV) microprocessor 40

41 Transistor Counts 1,000,000 K 1 Billion Transistors 100,000 10,000 1, i486 Pentium i Pentium III Pentium II Pentium Pro Courtesy, Intel Projected Source: Intel 41

42 Die Size Growth 100 Die size (mm) P6 Pentium proc ~7% growth per year ~2X growth in 10 years Year Die size grows by 14% to satisfy Moore s Law Courtesy, Intel 42

43 Frequency Frequency (Mhz) Doubles every 2 years P6 Pentium proc Year Lead Microprocessors frequency doubles every 2 years Courtesy, Intel 43

44 Power Dissipation Instantaneous power: p(t) = v(t)i(t) = V supply i(t) Peak power: P peak = V supply i peak Average power: 1 P ave = ) T V t+ T supply t+ T p( t dt = t t T i supply () t dt 44

45 Energy and Energy-Delay Power-Delay Product (PDP) = E = Energy per operation = P av t p Energy-Delay Product (EDP) = quality metric of gate = E t p 45

46 Power and Energy Figures of Merit Power consumption in Watts determines battery life in hours Peak power determines power ground wiring designs sets packaging limits impacts signal noise margin and reliability analysis Energy efficiency in Joules rate at which power is consumed over time Energy = power * delay Joules = Watts * seconds lower energy number means less power to perform a computation at the same frequency 46

47 Power versus Energy Watts Power is height of curve Lower power design could simply be slower Approach 1 Approach 2 Watts time Energy is area under curve Two approaches require the same energy Approach 1 Approach 2 time changing the operating frequency does not change the energy consumption 47

48 Power Dissipation 100 Power (Watts) P6 Pentium proc Year Lead Microprocessors power continues to increase Courtesy, Intel 48

49 MOSFET Feasibility 49

50 Power density Power Density (W/cm2) Rocket Nozzle Nuclear Reactor Hot Plate P6 Pentium proc Year Power density too high to keep junctions at low temp Courtesy, Intel 50

51 Die Cost Single die Wafer Going up to 12 (30cm) From 51

52 Average Cost per Transistor vs Time $ n$ 52

53 Why Scaling? Technology shrinks by 0.7/generation With every generation can integrate 2x more functions per chip; chip cost does not increase significantly Cost of a function decreases by 2x But How to design chips with more and more functions? Design engineering population does not double every two years Hence, a need for more efficient design methods Exploit different levels of abstraction 53

54 Design Abstraction Levels SYSTEM + MODULE GATE CIRCUIT S n+ G DEVICE n+ D 54

55 Design Abstraction At each design level, the internal details of a complex module can be abstracted away and replaced by a black-box view or model. This model contains virtually all the information needed to deal with the block at the next level of hierarchy. 55

56 Design Metrics How to evaluate performance of a digital circuit (gate, block, )? Cost Reliability Scalability Speed (delay, operating frequency) Power dissipation Energy to perform a function 56

57 DC Operation Voltage Transfer Characteristic V(y) V OH f V(y)=V(x) VOH = f(vol) VOL = f(voh) VM = f(vm) V M Switching Threshold V OL V OL V OH V(x) Nominal Voltage Levels 57

58 CMOS Inverter V DD V in V out C L 58

59 CMOS Inverter: Metrics COST: complexity and area INTEGRITY: static behavior ROBUSTNESS: noise margins PERFORMANCE: dynamic response EFFICIENCY: power consumption 59

60 CMOS Inverter: Steady State Response V DD V DD V OL = 0 V OH = V DD V M = f(r n, R p ) R p V out = 1 V out = 0 R n V in = 0 V in = V DD 60

61 CMOS Properties Full rail-to-rail swing high noise margins Logic levels not dependent upon the relative device sizes transistors can be minimum size ratioless Always a path to V dd or GND in steady state low output impedance (output resistance in kω range) large fan-out (albeit with degraded performance) Extremely high input resistance (gate of MOS transistor is near perfect insulator) nearly zero steady-state input current No direct path steady-state between power and ground no static power dissipation Propagation delay function of load capacitance and resistance of transistors 61

62 CMOS Inverter: Switch Model of Dynamic Behavior V DD V DD R p V out V out C L R n C L V in = 0 V in = V DD Gate response time is determined by the time to charge C L through R p (discharge C L through R n ) 62

63 Relative Transistor Sizing A fast gate is built either by keeping the output capacitances small or by decreasing the on-resistance of the transistors. When designing static CMOS circuits, balance the driving strengths of the transistors by making the PMOS section wider than the NMOS section to maximize the noise margins and obtain symmetrical characteristics 63

64 CMOS Inverter: Dynamic Transient, or dynamic, response determines the maximum speed at which a device can be operated. V DD V out = 0 We assume that V in is driven by an ideal voltage source with 0 rise and fall times. V in = V DD CL t phl = f(r n, C L ) R n We assume that all capacitances are lumped in one capacitor C L, between V out and GROUND. 64

65 Sources of Capacitance V in V out C L V out2 M 2 C DB2 C G4 M 4 Vin V out V out2 C GD12 C w M 1 C DB1 C G3 M 3 intrinsic MOS transistor capacitances extrinsic MOS transistor (fanout) capacitances wiring (interconnect) capacitance 65

66 Single Chip Microprocessors 250nm Pentium II (400MHz) 180nm Pentium III (1200MHz) 90nm Dual Core Opteron (2600MHz) 65nm Intel processor 66

67 Microelectronic in Telecommunications High Speed Viterbi processor Reed-Solomon Codec/Decoder FFT/IFFT Processor Analog Turbo Decoder 67

68 Single Chip Transceivers for wireless communications ZigBee (IEEE ) WiFi (IEEE b) WLAN (IEEE a) 68

69 Microelectronics in the automotive RF toll payment MEMS air flow sensor Collision avoidance radar Crash deceleration Pulse reader 69

70 Microelectronics in the aerospace The chip used in the Mars Explorer Rovers Chip Scale Atomic Clock for Aerospace Applications Space Shuttle thruster combustion chamber laser-scanning chip 70

71 Microelectronics for multimedia Picture-In-Picture (PIP) chip System-on-Chip (SoC) for Multimedia CMOS Digital-to-Analog Converter 71

72 Microelectronics for microbiology Carbon nanotubes chip for DNA analysis On chip Electrophoretic Devices for DNA Sequencing MEMS for bacterial detection Portable lab-on-a-chip system for detecting biological warfare agents floating 72

73 Advanced Metallization 73

74 Example: Intel 0.25 micron Process 5 metal layers Ti/Al - Cu/Ti/TiN Polysilicon dielectric 74

75 Bibliografia essenziale/1 A. S. Grove: Physics and Technology of Semiconductor Devices; Wiley S. M. Sze: VLSI Technology; 2nd., McGraw-Hill 1988 R. S. Muller, T. I. Kamins: Device Electronics for Integrated Circuits, 3rd ed., Wiley E. H. Nicollian, J. R. Brews: MOS (Metal Oxide Semiconductor) Physics and Technology, Wiley J. Rabaey, A. Chandrakasan, B. Nikolic: Digital Integrated Circuits, 2nd ed., Prentice Hall 2003 (in Italiano, 2005). 75

76 Bibliografia essenziale/2 A. Hastings: The art of Analog Layout; Prentice Hall P. Spirito: Elettronica Digitale; terza ed., McGraw-Hill